As computing systems have continued to develop, there has been a steady increase in the amount of memory resources available within a system for storing instructions and temporary or volatile data in the computing systems. All indications suggest that the trend will continue, and memory architectures will continue to expose more and more parallel resources to the memory controller. The parallel resources may include structures such as number of channels, bank groups, pages, and columns. The memory controller controls how access to the structures of the memory architecture is made.
Access to the structures of the memory architecture is controlled by memory mappings, which map physical memory addresses to the memory resources. Different memory mappings imply different latency, throughput, and power penalties. Current computing systems may have multiple possible mapping schemes, which function to control access to the memory resources in different ways. Current mapping schemes use static mapping tables that are selected at startup or reboot, and fixed for runtime of the computing system. The use of static mapping tables is inflexible and cannot take into account different load conditions that may only be apparent at runtime.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.